The invention pertains to a directory memory system, particularly, to a directory memory system which has the capability of simultaneously writing data into a memory block of the memory system and bypassing comparison input data onto an output data bus of the memory system.
Directory memory systems, especially directory memory systems fabricated upon a single integrated circuit chip, have recently found increasing use in high-speed computer systems. One example of such a directory memory system is disclosed in U.S. Pat. No. 4,219,883 to Kobayashi et al. Such devices can be used advantageously to perform a number of different functions within the computer system. One example is in a cache memory, which is a small, highspeed memory positioned between a main, slower memory and a central processor. The cache memory stores the most frequently used data retrieved by the processor from the main memory for rapid access by the processor. Another application of a directory memory chip is in a "trace" system in which a predetermined amount of the data most recently used by the processor is stored for examination to locate possible faults within the computer system. Many other applications of course are possible.
A directory memory chip should be capable of performing the following functions:
(1) writing input data into a memory block for temporary storage therein;
(2) reading data from the memory block onto an output data bus;
(3) comparing designated portions of the data stored in the memory block with received comparison data values; and
(4) bypassing the comparison data onto the output data bus.
Although prior art directory memory systems may have been capable of performing such functions, nevertheless, they suffered from a serious drawback in that none were capable of performing any of the above-mentioned functions simultaneously, specifically, functions which would not interfere with one another. More particularly, none were capable of performing the writing and bypassing functions simultaneously because the prior art directory memory systems generally caused the data present on the output lines of the output data bus to be invalid during data writing operations. This is disadvantageous in that memory or control cycles are wasted waiting for a writing operation to be completed before a bypassing operation can be commenced. The overall processing speed of a computer system employing one or more directory memory systems or chips could be significantly increased if the writing and bypassing operations could be performed simultaneously.
Accordingly, it is a primary object of the present invention to provide a directory memory system in which writing and bypassing operations can be performed simultaneously without interference with each other.